Shared Resources on Multicore Processors, Case Study Example

Managing Contention Problems for Shared Resources on Multicore Processors

Introduction

In the current multiprocessor technologies, there are improved capabilities of memory domains such as sharing of some common hardware structures as last-level caches, memory controllers in addition to other prefetching hardware. The study by Alexandria, Sergey and Simon on memory contention using different pairings led to various observations that can be critically analyzed.

Authors’ Findings

The solo execution of the four tasks developed a result that was viewed in terms of percentage of degradation. Each of the four applications was run individually on the system. In this case, Gamess and Namd recorded the highest performance since they had the least degree of degradation, while Soplex and Sphinx recorded lowest performance, with the highest degradation from the solo execution time.

The performance of a multiprocessor system depends on whether it is built on a contention-aware basis or on contention for shared resources approaches (Flynn, 1998). The combinations that were developed by the authors would be highly dependent on these two techniques. For instance, in the case where Soplex and Sphinx ran a memory domain, while Gamess and Namd were ran on the other domain, the ultimate result would be based on individual application requirements as well as the memory contention framework in use.

From the result that is obtained when each of the four applications were run solely, it is clear that they are likely to give different performance rates, irrespective of the architectural design used for the multicore system. In each of the designs that are used for the allocation of resources on the multicore system, the Operating System scheduler balances CPU time in order to minimize on the idling of any of the cores. For instance, in a case of a system with four cores, a thread-based scheduler will be used, and in this case each of the four cores will independently cache recently used directions. The future trends in multicore systems is associated with development of contention-aware architectures in which multiple tasks will be performed without delays in the performance of application programs.

Analysis of Schedules

The authors used different architectures to test for the applications. In the tests, they put into operation contention-aware schedules and contention oblivious schedulers. According to the authors, a contention-oblivious scheduler may also run the best schedule; it was more advisable to run applications on contention-aware schedules. The contention-aware schedules are associated with multiple advantages over the other schedules.

Contention-aware schedules are often associated with improved performance levels. The assignment problems that are associated with the other schedules are not so pronounced with the contention-aware scheduling techniques. The capabilities of the contention-aware schedules made the authors grade it as the best schedule.

Findings on Cache Contention

The authors’ findings on cache contention attributed the contention to two or more threads being assigned to run on the same core domains simultaneously. In the current multi-core systems, cache contention arises mainly as a result of true and false sharing that leads to unexpected significant performance degradation.

In a detailed analysis, the issues behind cache contention may come along where the cache is full. In this case, all the cache lines are being used to hold different sets of data. Consequently, some of the cache lines have to be freed through eviction of some pieces of data to allow for processing of new data.

The analysis bases argument from two schools of thought. The first one that considers the last-level cache (LLC) miss rate as a good technique of predicting whether the data threads are likely to compete for memory allocation. In this school of thought, the logic is that if a thread is associated with lots of cache misses, there has to be a large cache working set. In the case of cache misses, there is need for allocation of new cache lines. The designs that are associated with cache contentions from this point of view are those that have large cache working sets.

The believers in the second school of thought, according to the authors, suggest that if a single threat rarely reuses the cached data, it will experience cache contention issues (Chen, Dick & Mao, 2011). This directly contradicts the idea as suggested by the first school of thought. The argument from the second school of thought is that the thread will require very little space to cache the data that it uses most frequently when it is active.

Those that follow the second school of thought have come up with various models for shared cache contentions that are based on memory re-use patterns. The memory re-use patterns are based on the memory re-use profile, commonly known as the re-used distance profile.

Contention Prevention Methods

There are three main solutions that have been proposed by the authors as solutions to contention problems in multiprocessor and multi-core systems. These are briefly discussed below.

1. Front-Side Bus (FSB). The FSB is a connector between the computer’s processor and the system memory (Random Access Memory) to other components of the motherboard. The components that are interconnected with the FSB include chipset, Personal Computer interface devices, and other peripheral devices. The FSB is associated with increasing the speed with which data transmission and processing is accelerated. In so doing, contention problems are well taken care of.
2. Memory Controller. The memory controller for multicore systems helps to control traffic among multiple core packs. It also enables sharing of processing resources to prevent contention problems (Zhao et al, 2011). The use of memory controllers as a way of protecting the memory from the challenges associated with contentions, especially to the cache. The memory controller types used depend on the multicore schedules that are put into operations. This directly determines their levels of efficiency.

• Prefetching hardware in the distributed architecture. This solution is mainly recommended for read-miss issues that are associated with the arguments of the first school of thought on cache contention. Sequential prefetching is a hardware-regulated prefetching technique that relies heavily on automatic pre-fetch, especially for consecutive and repetitive applications. Pre-fetching hardware helps to reduce contention through automation of repetitive sequential tasks on the multi-core systems.

Conclusion

Multi-core systems are associated with contention issues that require appropriate schedules for effective performance. The construction of contention-aware schedules for the multi-core processors is often associated with the best possible assignment of tasks. The solutions put forward by the authors as solutions to cache contention issues are appropriate depending on the schedulers that are put into operation. The effective application of the FSB, for instance, depends on the hardware configuration, to cater for the sequential operation of the applications. Elimination of data misses from the second school of thought will rely more on prefetching hardware.

References

Chen, C. X, Dick, R. P & Mao, Z. M. (2011). Cache Contention and Application Performance Prediction for Multi-Core Systems. Minnesota. University of Minnesota. From http://web.eecs.umich.edu/~zmao/Papers/xu10mar.pdf

Flynn, M. J. (1998). Computer architecture: Pipelined and parallel processor design. Boston [u.a.: Jones and Bartlett.

Keckler, S. W., Olukotun, O. A., & Hofstee, H. P. (2009). Multicore processors and systems. New York: Springer.

Zhao, Q., Koh, R., Bruening, D., Wong, F. W. & Amarasinghe, S. (2011). Dynamic Cache Contention Detection in Multi-threaded Application. Massachusettes. Google Inc From http://groups.csail.mit.edu/commit/papers/2011/zhao-vee11-cache-contention.pdf